At this time there is one research project, based on encryption. The goal is to create a digital system, which includes custom CPUs, custom PCB and proprietary software, wich will break a number of chiphers in the fastest manner. The good example of such system is "Copacobana" project.
This course was developed for 4-th year students who are starting to learn the basics of digital design. The course covers basics of RTL (Register Transfer Level) design with Verilog HDL language for FPGA (Field-Programming Gate Arrays). It also covers some simple verification techniques like test vectors, waveforms analysis and so on. In practical part of the course, students develope their code using Xilinx tools, like ISE, and Xilinx hardware kit - Atlys. Atlys is the cutting edge offer from Xilinx for the universities with the purpose of giving up-to-date technology to the students. The students in turn could understand the basic concepts of digital world working with the best software and chips.
This course is also provided for 4-th year students, but for second half of the year. During the course students make a project from scratch, which consists of: RTL for CPU, ISA (Instruction Set Architecture) model of CPU, assembler, verification components and some software to link the CPU with the computer (for example, using RS232 port). Students use different programming and hardware languages, like: Verilog HDL, SystemVerilog, C/C++, Perl, Python, etc.